Nonvolatile memories, known as flash memory devices, have become very popular in a variety of uses including mobile phones, digital answering machines, and personal digital voice recorders. Low pin count, low cost, and ease-of-use are key factors for the wide utilization of flash memory.
A flash memory may be divided into sectors at the highest level, where each sector is composed of multiple blocks, each block is composed of multiple pages, and each page is composed of hundreds of bytes. Flash memories allow for erasing, programming, and reading at the block, page, and byte level. For example, a single command may erase an entire block or page of memory.
Contents of a sequential type of flash memory may be accessed by supplying an initial address and applying a number of clock cycles equal to the number of sequential addresses desired for access in a memory operation. An internal address counter automatically increments an access address with each clock. This avoids any requirement of additional address sequencing externally. This capability allows sequential reading to cross page and sector boundaries seamlessly.
To conduct a continuous read operation, a read command is given which includes a starting memory address. After allowing a period of time for internal read operations and address decoding, a first byte of data is available commencing from the initial address given. Data from sequential addresses are available with each successive clock cycle. A drawback of reading continuously from prior sequential memories has been the amount of latency after a read command is entered until data are output. The delay from read command input and data output degrades an efficiency of continuous read operations.
With reference to FIG. 1A, a prior art nonvolatile memory 100 contains a memory array 105 including bit memory blocks 115 organized in parallel to form data words. There is a bit memory block 115 per output of the memory array 105. An output of each bit memory block 115 connects to an element of a sense amp register 120. An output of the sense amp register 120 connects to a serial data register 130. An output of the serial data register 130 connects to a serial output 135 of the nonvolatile memory 100.
A clock generator 155 receives a clock signal from a serial clock input 160. A serial data input 145 of the nonvolatile memory 100 connects to a controller 140. Commands, addresses, and data are received through the serial data input 145. The controller 140 provides control input to the clock generator 155, the sense amp register 120, and an address decoder 150.
The controller 140 receives a continuous read command followed by three bytes of address information. After decoding the continuous read command, the controller 140 and address decoder 150 determine a target data byte and connect the appropriate bits of the memory array 105 to the sense amp register 120. The first two address bytes received determine a target data byte location to the sector, block, and page level.
The byte address, the third byte, is used to to completely address the target data byte. Complete address decoding and establishment of read voltages occurs during a period of four dummy bytes occurring between the time the byte address is completely received and the first byte of data is output. Three clock lines from the clock generator 155 connect to the serial data register 130 to control which bit positions are shifted out of the serial output 135.
With reference to FIG. 1B, a prior art nonvolatile memory 110 contains a memory array 105, clock generator 155, address decoder 150, sense amp register 120, serial data register 130, and controller 140 connected as discussed supra (FIG. 1A). The inputs of a multiplexer 133 connect to a set of respective outputs of the serial data register 130. Three output lines of the clock generator 155 are encoded to select one of eight possible values. A selection of the inputs to the multiplexer is sequenced through under control of the signal values on the three clock lines from the clock generator 155. A high order clock line 153 connects to the serial data register 130 to control latching of data every eight clock cycles. An output of a multiplexer 133 connects to the serial output 135.
With reference to FIG. 2, in a continuous read operation waveform diagram 200 of the prior art, a bit stream at serial data input 145 (FIG. 1) contains a command byte 210, followed by three address bytes 220, followed by four dummy bytes 230. After receipt of the fourth dummy byte, the serial output produces the first data byte 240 available at the serial output 135. Successive target data bytes are clocked out in a similar fashion until the continuous read operation concludes.
For a system utilizing flash memories with multiple continuous read operations, the amount of latency between the read command and data output is a significant impact to overall system efficiency. A desirable operation of flash memory would be to submit a continuous read operation command and have the data available immediately after the command is entered.